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Show moreBackground of the invention: The present invention relates to the art of random access memories. It finds particular application in connection the testing of large scale memories and will be described with particular reference thereto. The invention will also find uses in other applications of electronic memories. A significant amount of work has been done in the recent years to obtain fast and very large memory systems. As a result, the density of semiconductor memory chips has increased dramatically. The increase in density and size of the memories has resulted in a corresponding increase in the difficulty of testing of such memories. A multi-mega bit random access memory (RAM) requires extended amounts of time in order to test cell stuck-at faults and other varieties of possible faults. To overcome this problem, two general approaches have been developed. First, researchers have attempted to develop efficient test generation methods, and second, memories including built-in self-testing capabilities have been proposed. Several innovative test methods for random access memories have been reported. These methods can be categorized into two classes; One set of methods are based on a stuck-at fault model. Representative examples of proposed methods based on this model include, J. Knaizuk and C. R. P. Hartman, "An optimal method for testing stuck-at faults in ransom access memories", IEEE Trans. Comp., vol. 26(11) , pp. 1141-1144, November 1977; R. Nair, S. M. Thatte and J. A. Abraham, "Efficient methods for testing semiconductor random access memories", IEEE Trans. Comp., vol. 27(6), pp. 572-576, June 1978; R. Nair, "Comments on an optimal method for testing stuck-at faults in random access memories", IEEE Trans. Comp., vol. 28(3) , pp. 258-261, March 1979; R. Dekker, F. Beenker and L. Thijssen, "A realistic fault model and test method for static random access memories", IEEE Trans. CAD, vol. 9(6), pp. 567-572, June 1990; R. Dekker, F. Beenker and L. Thijssen, "Fault modeling and test method development for static random access memories", Proc. Int. Pest Conf., pp. 343-352, 1988; A. Birolini, W. Buchel and D. Heavner, "Test and screening strategies for large memories", Proc. European Test Conf., pp. 276-283, 1989; T. Fuja, C. Heegard and R. Goodman, "Linear sum codes for random access memories", IEEE Trans. Comp. , vol 37(9) , pp. 1030-1042, September 1988; C. A. Papachristou and N. B. Sahgal, "An improved method for detecting functional faults in semiconductor random access memories", IEEE Trans. Comp., vol. 34(2), pp. 110-116, February 1975; J. Savir, W. H. McAnney and S. R. Vecchio, "Fault propagation through embedded multiport memories", IEEE Trans. Comp., vol. 36(5), pp. 592-602, May 1987; R. David, A. Fuentes and B. Courtois
http://www.google.com/patents?vid=USPAT5377148
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